1. Field of the Present Invention
The present invention generally relates to the field of input/output (I/O) busses and more particularly to a system for monitoring the performance of PCI-X and PCI bridges.
2. History of Related Art
In the field of microprocessor based data processing systems, the use of industry standard busses to improve the performance and expand the capabilities of the data processing systems is well known. Standardized I/O busses provide a mechanism for connecting a wide variety of peripheral devices to the host bus of a data processing system. Peripheral devices may include, for example, high speed network adapters, hard-disk controllers, graphics adapters, audio adapters, and a variety of other devices. Among the most prevalent of the industry standard I/O busses is the Peripheral Component Interface (PCI) bus. The PCI bus has evolved over the years from revision 2.0 introduced in 1992 operating at a bus frequency of 33 MHz, to revision 2.1 introduced in 1995 with a maximum bus frequency of 66 MHz, to revision 2.2 introduced in 1998 and incorporating features such as message interrupts. Complete documentation of the PCI Local Bus Specification Rev. 2.2 (PCI Spec 2.2) is available from the PCI special interest group, 2575 N.E. Kathryn #17, Hillsboro, Oreg. 97124 (website www.pcisig.com). Under PCI Spec 2.2, PCI bridges support two types of transactions: posted transactions (including memory write cycles), which complete on the initiating bus before they complete on the target bus, and delayed transactions (including memory read requests and I/O and configuration read/write requests), which complete on the target bus before they complete on the initiating bus. A PCI device that initiates a delayed transaction must relinquish control of the local PCI bus and wait for the target device to return the requested data (in the case of a delayed read request) or a completion message (in the case of a delayed write request). Once the requested information has arrived, the requesting device must wait until it again receives control of the PCI bus in the normal course of operations before it can retrieve the information from the PCI bridge.
More recently, the PCI-X Addendum to Local Bus Specification Rev. 2.2 has been proposed as a means for further improving the performance of PCI busses. The PCI-X Addendum incorporates registered transactions that improve performance by permitting a PCI-X compatible bridge or I/O adapter to make decisions on every other clock cycle. In addition, PCI-X incorporates protocol enhancements such as the attribute phase and split transactions that allow more efficient use of the bus. PCI-X is fully backward compatible with conventional PCI systems such that conventional PCI adapters will work in PCI-X capable systems and PCI-X adapters will work in PCI systems. If a conventional PCI device is located on a PCI-X bus, however, all adapters on the bus must operate in conventional PCI mode regardless of whether they are PCI-X capable. For complete PCI-X documentation, the reader is referred to the PCI-X Addendum 1.0 Final Release available from the PCI Special Interest Group.
The architectures of state-of-the-art microprocessors now typically incorporate mechanisms for some level of performance monitoring capability. Performance monitors in highly complex microprocessors are needed to measure the efficiency of a particular design and provide valuable information that enables a designer to modify a current system and improve future systems. In a microprocessor application, a performance monitor might, for example, monitor various aspects of the cache system such as the read miss rate. As processor performance has improved, the I/O subsystem, including I/O bridges such as host-to-PCI and host-to-PCI-X bridges as well as PCI-to-PCI and PCI-X-to PCI-X bridges, have become the bottlenecks for system throughput. Efforts to combat this I/O bottleneck problem has resulted in ever increasingly complex I/O bridge designs. Despite the increasing complexity of I/O bridge designs, however, there is currently lacking a mechanism or architecture within the bridges themselves that would enable embedded and flexible I/O subsystem performance monitoring. Accordingly, it would be highly desirable to implement an I/O bus bridge with performance monitoring capabilities. It would be further desirable if the implemented design was flexible, did not consume a significant percentage (area) of the I/O bridge design, and did not significantly degrade the performance of the bridge.
The problems identified above are addressed by a bus bridge of a data processing system in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus. The bridge may monitor events such as accepting a posted memory write (PMW), accepting with split response a read request (RR), retrying a PMW, retrying a RR, disconnecting a PMW when the bridge is a target of the operation. When the bridge is the master of an operation, the bridge may monitor the target accepting a PMW, accepting a split read completion operation (SRC), accepting a RR with split response, accepting a split write request operation (SWR) with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, and disconnecting a SRC. In a PCI-X to PCI-X embodiment of the bridge, the bridge may monitor the primary and secondary busses are PCI-X or PCI busses and the events monitored including accepting a PMW, accepting a SRC, accepting a RR with spilt response, accepting a SWR with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is the target of an operation. When the bridge is a master of the operation, the bridge may monitor the target accepting a PMW, accepting a SRC, accepting a RR with split response, accepting a SWR with split response, accepting a RR with immediate response, accepting a SWR with immediate response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC. In either embodiment, the bridge may further include a mode register corresponding to each performance monitor register where the value of the mode register determines the specified activity monitored by the corresponding performance monitor register.
The mode and counter registers are software accessible, such that it is possible to write an application that will setup the I/O performance monitor hardware for counting certain events of interest and for reading the results after a certain period of time or a specified number of events has elapsed. After the software has captured a number of these samples, the software can analyze the data to assist system and chip designers to tune their designs for better performance.